digraph fir { node [fontcolor=white,style=filled,color=blue2]; MUL_0 [label = MUL ]; MUL_1 [label = MUL ]; MUL_2 [label = MUL ]; MUL_3 [label = MUL ]; MUL_4 [label = MUL ]; MUL_5 [label = MUL ]; MUL_6 [label = MUL ]; MUL_7 [label = MUL ]; MUL_8 [label = MUL ]; MUL_9 [label = MUL ]; MUL_10 [label = MUL ]; ADD_11 [label = ADD ]; ADD_12 [label = ADD ]; ADD_13 [label = ADD ]; ADD_14 [label = ADD ]; ADD_15 [label = ADD ]; ADD_16 [label = ADD ]; ADD_17 [label = ADD ]; ADD_18 [label = ADD ]; ADD_19 [label = ADD ]; ADD_20 [label = ADD ]; IN_12 [label = MemR ]; COF_13 [label = MemR ]; IN_14 [label = MemR ]; COF_15 [label = MemR ]; IN_16 [label = MemR ]; COF_17 [label = MemR ]; IN_18 [label = MemR ]; COF_19 [label = MemR ]; IN_20 [label = MemR ]; COF_21 [label = MemR ]; IN_22 [label = MemR ]; COF_23 [label = MemR ]; IN_24 [label = MemR ]; COF_25 [label = MemR ]; IN_26 [label = MemR ]; COF_27 [label = MemR ]; IN_28 [label = MemR ]; COF_29 [label = MemR ]; IN_30 [label = MemR ]; COF_31 [label = MemR ]; IN_32 [label = MemR ]; COF_33 [label = MemR ]; OUT_1 [label = MemW ]; IN_12 -> MUL_0 [ name = 0 ]; COF_13 -> MUL_0 [ name = 1 ]; IN_14 -> MUL_1 [ name = 2 ]; COF_15 -> MUL_1 [ name = 3 ]; IN_16 -> MUL_2 [ name = 4 ]; COF_17 -> MUL_2 [ name = 5 ]; MUL_0 -> ADD_11 [ name = 6 ]; MUL_1 -> ADD_11 [ name = 7 ]; ADD_11 -> ADD_12 [ name = 8 ]; MUL_2 -> ADD_12 [ name = 9 ]; IN_18 -> MUL_3 [ name = 10 ]; COF_19 -> MUL_3 [ name = 11 ]; IN_20 -> MUL_4 [ name = 12 ]; COF_21 -> MUL_4 [ name = 13 ]; IN_22 -> MUL_5 [ name = 14 ]; COF_23 -> MUL_5 [ name = 15 ]; MUL_3 -> ADD_13 [ name = 16 ]; MUL_4 -> ADD_13 [ name = 17 ]; MUL_5 -> ADD_14 [ name = 18 ]; ADD_12 -> ADD_14 [ name = 19 ]; ADD_13 -> ADD_15 [ name = 20 ]; ADD_14 -> ADD_15 [ name = 21 ]; IN_24 -> MUL_6 [ name = 22 ]; COF_25 -> MUL_6 [ name = 23 ]; IN_26 -> MUL_7 [ name = 24 ]; COF_27 -> MUL_7 [ name = 25 ]; IN_28 -> MUL_8 [ name = 26 ]; COF_29 -> MUL_8 [ name = 27 ]; ADD_15 -> ADD_16 [ name = 28 ]; MUL_8 -> ADD_16 [ name = 29 ]; MUL_6 -> ADD_17 [ name = 30 ]; MUL_7 -> ADD_17 [ name = 31 ]; ADD_17 -> ADD_18 [ name = 32 ]; ADD_16 -> ADD_18 [ name = 33 ]; IN_30 -> MUL_9 [ name = 34 ]; COF_31 -> MUL_9 [ name = 35 ]; IN_32 -> MUL_10 [ name = 36 ]; COF_33 -> MUL_10 [ name = 37 ]; ADD_18 -> ADD_19 [ name = 38 ]; MUL_9 -> ADD_19 [ name = 39 ]; MUL_10 -> ADD_20 [ name = 40 ]; ADD_19 -> ADD_20 [ name = 41 ]; ADD_20 -> OUT_1 [ name = 42 ]; }