ExPRESS Group
Extensible, Programmable and Reconfigurable
Embedded SystemS Group
Publications
Books
[B1] Ryan Kastner, Adam Kaplan and Majid Sarrafzadeh, "Synthesis Techniques and Optimizations for Reconfigurable Systems", Kluwer Academic Publishers, November 2003, ISBN 1-4020-7598-3 (order)
[B2] Anup Hosangadi, Farzan Fallah and Ryan Kastner , "Arithmetic Optimization Techniques for Hardware and Software Design", Cambridge University Press, to appear
Patents
[P1] Farzan Fallah, Anup Hosangadi and Ryan Kastner, "System and Method for Optimizing Polynomial Expressions in a Processing Environment ", provisional application serial number 11/084,358 filed March 17, 2005
[P2] Farzan Fallah, Anup Hosangadi and Ryan Kastner, "System and Method for Eliminating Common Subexpressions in a Linear System", provisional application #20060294169
[P3] Farzan Fallah, Anup Hosangadi and Ryan Kastner, "System and Method for Iteratively Eliminating Common Subexpressions in an Arithmetic System", provisional application filed, January 13, 2006
Journal Publications
[J1] Kiarash Bazargan, Ryan
Kastner and Majid Sarrafzadeh, "Fast
Template Placement for Reconfigurable Computing Systems", IEEE
Design and Test - Special Issue on Reconfigurable Computing, January
-
March 2000 (pdf)
[J2] Kiarash Bazargan, Ryan
Kastner and Majid Sarrafzadeh, "3-D
Floorplanning: Simulated Annealing and Greedy Placement Methods for
Reconfigurable Computing Systems", Design Automation
for Embedded Systems - RSP'99 Special
Issue, August 2000 (pdf)
[J3] Ankur Srivastava, Ryan
Kastner and Majid Sarrafzadeh, "On
the Complexity
of Gate Duplication", IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems,
September
2001 (pdf)
[J4] Xiaojian Yang, Ryan
Kastner and Majid Sarrafzadeh, "Congestion
Estimation During Top-down Placement", IEEE Transactions
on
Computer-Aided Design of Integrated Circuits and Systems, January
2002 (pdf)
[J5] Ryan Kastner, Elaheh
Bozorgzadeh and Majid Sarrafzadeh, "Pattern
Routing: Use and Theory for Increasing Predictability and Avoiding
Coupling",
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and
Systems, July 2002 (pdf)
[J6] Ryan Kastner, Adam
Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh, "Instruction Generation for Hybrid
Reconfigurable Systems",
ACM Transactions on Design Automation of Electronic Systems,
October,
2002 (pdf)
[J7] Elaheh Bozorgzadeh,
Ryan Kastner and Majid Sarrafzadeh, "Creating
and Exploiting Flexibility in Steiner Trees", IEEE
Transactions on Computer-Aided Design of Integrated Circuits and
Systems, May 2003 (pdf)
[J8] Xiaojian Yang, Maogang
Wang, Ryan Kastner, Soheil Ghiasi and Majid Sarrafzadeh,
"Congestion Reduction during
Placement with
Provably Good Approximation Bound", ACM Transactions on
Design Automation of Electronic Systems, July 2003 (pdf)
[J9] Ankur Srivastava, Ryan
Kastner, Chunhong Chen and Majid Sarrafzadeh, "Timing
Driven Gate Duplication", IEEE Transactions on Very
Large Scale
Integrated Systems, Jan.
2004 (pdf)
[J10]
Seda Ogrenci Memik, Ryan Kastner, Elaheh
Bozorgzadeh, and Majid Sarrafzadeh, "A Scheduling Algorithm
for Optimization
and Planning in High-level Synthesis",
ACM Transactions on Design Automation of
Electronic Systems, Vol. 10,
No. 1,
January 2005 (pdf)
[J11] Yan Meng, Timothy Sherwood and Ryan
Kastner, “Exploring the
Limits of Leakage Power Reduction in Caches”, ACM
Transactions on Architecture and Code Optimization, November
2005 (pdf)
[J12] Yan
Meng, Wenrui Gong, Ryan Kastner and Timothy
Sherwood, “Algorithm/Architecture
Co-exploration for Designing Energy
Efficient Channel Estimator” –
American Scientific Publishers Journal of Low Power Electronics,
December 2005 (pdf)
[J13] Gang Wang, Wenrui Gong and Ryan
Kastner, “Application
Partitioning on Programmable Platforms Using the Ant Colony
Optimization”, Journal
of
Embedded Computing, Vol. 2, Issue 1, 2006 (pdf)
[J14] Gang Wang, Satish Sivaswamy, Cristinel
Ababei,
Kia Bazargan, Ryan Kastner and Elaheh Bozorgzadeh, “Statistical
Analysis and Design of Hardwired Routing Pattern FPGAs”, IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol.
25, no. 10, Oct. 2006, pp. 2088-102 (pdf)
[J15] Anup Hosangadi, Farzan Fallah and Ryan
Kastner, “Optimizing
Polynomial Expressions by Algebraic Factorization and Common
Subexpression
Elimination”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. 25, no.
10, Oct. 2006, pp. 2012-22 (pdf)
[J16] Gang Wang, Wenrui Gong, Brian DeRenzi
and Ryan
Kastner, “Ant Colony
Optimizations for Resource- and Timing-Constrained
Operation Scheduling” – IEEE Transactions on Computer-Aided Design, vol. 26, no. 26, June 2007, pp. 1010-29 (pdf)
[J17] Anup Hosangadi, Farzan Fallah and Ryan
Kastner, “Algebraic
Methods for Optimizing Constant Multiplications in Linear Systems”, to appear in the Springer
Journal of VLSI Signal Processing,
(preliminary pdf)
[J18] Gang Wang, Wenrui Gong, Brian DeRenzi
and Ryan
Kastner, “Exploring
Time/Resource Tradeoffs by Solving Dual Scheduling
Problems with the Ant Colony Optimization” – to appear in the ACM
Transactions
on Design Automation of Electronic Systems
Book Chapters
[BC1] Elaheh Bozorgzadeh, Ryan Kastner, Seda Ogrenci Memik and Majid Sarrafzadeh, "Strategically Programmable Systems", The Computer Engineering Handbook, CRC Press, December 2001
[BC2] Elaheh Bozorgzadeh, Adam Kaplan, Ryan Kastner, Seda Ogrenci Memik and Majid Sarrafzadeh, "Optimization for Reconfigurable Systems Using Hierarchical Abstraction", Multi-level Optimization and VLSI CAD, J. Cong and J. R. Shinnerl (editors), Kluwer Academic Publishers, Boston, 2002 (pdf)
[BC3] Gang Wang, Wenrui Gong, and Ryan Kastner, "Operation Scheduling: Algorithms and Design Space Exploration", High Level Synthesis: From Algorithm to Digital Circuit, Springer Publishing Company, to appear
Refereed Conference Publications
[C1] Kiarash
Bazargan, Ryan Kastner and Majid
Sarrafzadeh, "3-D
Floorplanning: Simulated
Annealing and Greedy Placement Methods for Reconfigurable Computing
Systems",
International Workshop on Rapid System Prototyping (RSP),
June 1999 (pdf)
[C2] Ryan
Kastner, Kiarash Bazargan and Majid
Sarrafzadeh, "Physical Design
for
Reconfigurable Computing Systems using Firm Templates", Workshop
on Reconfigurable Computing (WoRC), October 1999 (pdf,
slides)
[C3] Kiarash Bazargan, Ryan Kastner, Seda Ogrenci
and Majid Sarrafzadeh, "A C to
Hardware/Software Compiler", Symposium on
Field-Programmable
Custom Computing Machines (FCCM), April 2000 (pdf)
– poster presentation
[C4] Ankur
Srivastava, Ryan Kastner and Majid
Sarrafzadeh, "Complexity Issues
in Gate
Duplication", International Workshop on Logic Synthesis
(IWLS), June 2000 (pdf)
[C5] Ryan
Kastner, Elaheh Bozorgzadeh and Majid
Sarrafzadeh, "Coupling Aware
Routing",
International ASIC/SOC Conference, September 2000 (pdf,
slides)
[C6] Ankur
Srivastava, Ryan Kastner and Majid Sarrafzadeh,
"Timing Driven Gate
Duplication: Complexity
Issues and Algorithms", International Conference on
Computer-Aided Design (ICCAD), November 2000 (pdf,
slides)
[C7] Ryan
Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh, "Predictable Routing", International
Conference on Computer-Aided Design (ICCAD), November 2000 (pdf,
slides)
[C8] Seda
Ogrenci Memik, Elaheh Bozorgzadeh, Ryan
Kastner and Majid Sarrafzadeh, "Strategically
Programmable Systems", Reconfigurable Architecture
Workshop
(RAW), April 2001 (pdf)
[C9] Majid
Sarrafzadeh, Elaheh Bozorgzadeh, Ryan Kastner and Ankur Srivastava, "Design and Analysis of Physical Design
Algorithms",
International Symposium on Physical Design (ISPD), April
2001 (pdf,
slides)
[C10] Xiaojian Yang, Ryan
Kastner and Majid Sarrafzadeh, "Congestion
Estimation during Top-down Placement", International
Symposium on Physical Design (ISPD), April 2001 (pdf,
slides)
[C11] Ryan Kastner, Elaheh
Bozorgzadeh and Majid Sarrafzadeh, "An
Exact Algorithm for Coupling-Free Routing", International
Symposium on Physical Design (ISPD), April 2001 (pdf,
slides)
[C12] Elaheh Bozorgzadeh,
Ryan Kastner and Majid Sarrafzadeh, "Creating
and Exploiting Flexibility in Steiner Trees", Design
Automation Conference (DAC), June 2001 (pdf,
slides)
[C13] Andrew B. Kahng, Ryan
Kastner, Stefanus Mantik, Majid Sarrafzadeh and Xiaojian Yang, "Studies of Timing Structural Properties
for Early
Evaluation of Circuit Design", Workshop on Synthesis and
System Integration of Mixed Technologies (SASIMI), October 2001 (pdf,
slides)
[C14] Xiaojian Yang, Ryan
Kastner and Majid Sarrafzadeh, "Congestion
Reduction During Placement Based on Integer Programming", International
Conference on Computer-Aided Design (ICCAD), November 2001 (pdf,
slides)
[C15] Seda Ogrenci Memik,
Elaheh Bozorgzadeh, Ryan Kastner and Majid Sarrafzadeh, "A Super-Scheduler for Embedded
Reconfigurable Systems",
International Conference on Computer-Aided Design (ICCAD), November
2001
(pdf)
[C16] Ryan Kastner, Seda
Ogrenci Memik, Elaheh Bozorgzadeh and Majid Sarrafzadeh, "Instruction Generation for Hybrid
Reconfigurable Systems",
International Conference on Computer-Aided Design (ICCAD),
November 2001
(pdf,
slides)
[C17] Elaheh Bozorgzadeh,
Seda Ogrenci Memik, Ryan Kastner, and Majid Sarrafzadeh, "Pattern Selection in Programmable
Systems
", International Symposium of Field
Programmable Gate Arrays (FPGA), February 2002 (pdf)
–
poster presentation
[C18] Elaheh Bozorgzadeh,
Seda Ogrenci Memik, Ryan Kastner and Majid Sarrafzadeh, "Pattern Selection: Customized Block
Allocation for
Domain-Specific Programmable Systems", International
Conference on Engineering of Reconfigurable Systems and Algorithms
(ERSA), June
2002 (pdf)
[C19] Ryan Kastner,
Christina Hsieh, Miodrag Potkonjak and Majid Sarrafzadeh, "On the Sensitivity of Incremental
Algorithms for
Combinatorial Auctions", International Workshop on
Advanced
Issues of E-Commerce & Web-Based Information Systems (WECWIS), June
2002 (pdf,
slides)
[C20] Philip Brisk, Adam
Kaplan, Ryan Kastner and Majid Sarrafzadeh, "Instruction
Generation and Regularity Extraction for Reconfigurable Processors",
International Conference on Compilers, Architecture and
Synthesis for
Embedded Systems (CASES), October 2002 (pdf,
slides)
[C21] Adam Kaplan, Majid
Sarrafzadeh and Ryan Kastner, “High-Level
Data
Communication Optimization for Reconfigurable Systems", Workshop
on Software Support for Reconfigurable Systems (SSRS),
co-located with the International
Symposium on High-Performance Computer Architecture (HPCA), February
2003 (pdf)
[C22] Adam Kaplan, Philip
Brisk and Ryan Kastner, “Data
Communication
Estimation and Reduction for Reconfigurable Systems", Design
Automation Conference (DAC), June
2003 (pdf,
slides)
[C23] Gang Wang, Wenrui Gong and Ryan
Kastner, “A New Approach for
Task Level Computational Resource
Bi-partitioning”, IASTED
International Conference on Parallel and Distributed Computing and
Systems (PDCS),
November 2003 (pdf,
slides)
– Best paper nomination
[C24] Wenrui Gong, Gang Wang and Ryan
Kastner, “A High
Performance Intermediate Representation for Reconfigurable Systems”, International Conference on
Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2004 (pdf,
slides)
[C25] Anup Hosangadi, Farzan Fallah and Ryan
Kastner,
“Optimizing
Polynomial Expressions by Factoring and Eliminating Common
Subexpressions”, International
Workshop on
Logic and Synthesis (IWLS),
June 2004 (pdf)
[C26] Gang Wang, Wenrui Gong and Ryan
Kastner, “System Level
Partitioning for Programmable Platforms Using the Ant Colony
Optimization”, International
Workshop on
Logic and Synthesis (IWLS),
June 2004 (pdf)
– poster presentation
[C27] Anup Hosangadi, Farzan Fallah and Ryan
Kastner,
“Common
Subexpression Elimination Involving Multiple Variables for Linear DSP
Synthesis”
International
Conference on Application-specific
Systems, Architectures and Processors, September 2004 (pdf,
slides)
[C28] Anup Hosangadi, Farzan Fallah and Ryan
Kastner,
“Factoring
and Eliminating Common Subexpressions in Polynomial Expressions”, International Conference on
Computer-Aided Design (ICCAD),
November 2004 (pdf,
slides)
[C29] Anup Hosangadi, Farzan Fallah and Ryan
Kastner,
“Energy
Efficient Hardware Synthesis of Polynomial Expressions”, International
Conference on VLSI Design, January 2005
(pdf,
slides)
- N. N. Biswas Best Student Paper
Award
[C30] Anup Hosangadi, Farzan Fallah and Ryan
Kastner,
“Reducing
Hardware Complexity of Linear DSP Systems by Iteratively Eliminating
Two Term
Common Subexpressions”,
[C31] Yan Meng, Timothy Sherwood and Ryan
Kastner, “On the Limits
of Leakage Power Reduction in Caches”,
International Symposium on
High-Performance Computer Architecture (HPCA), February 2005 (pdf,
slides)
[C32] Satish Sivaswamy, Gang Wang, Cristinel
Ababei,
Kia Bazargan, Ryan Kastner and Elaheh Bozorgzadeh, “HARP:
Hard-wired Routing Pattern FPGAS”, International Symposium on
Field
Programmable Gate Arrays (FPGA), February 2005 (pdf,
slides)
[C33] Gang Wang, Wenrui Gong and Ryan
Kastner, “Instruction
Scheduling Using MAX- MIN Ant Colony Optimization”, Great Lakes
Symposium on Very Large Scale Integration (GLSVLSI), April 2005
(pdf,
slides)
[C34] Anup Hosangadi, Farzan Fallah and Ryan
Kastner, “Simultaneous
Optimization of Delay and Number of Operations in Multiplierless
Implementation
of Linear Systems” – International
Workshop on Logic and Synthesis (IWLS), June 2005 (pdf)
– poster presentation
[C35] Ryan Kastner, Wenrui Gong, Xin Hao,
Forrest
Brewer, Adam Kaplan, Philip Brisk and Majid Sarrafzadeh, “Physically
Aware Data Communication Optimization for Hardware Synthesis” –International
Workshop on Logic and Synthesis (IWLS), June 2005 (pdf,
slides)
[C36] Wenrui Gong, Gang Wang and Ryan
Kastner, “Data
Partitioning for Reconfigurable Architectures with Distributed Block
RAM” – International Workshop on Logic and Synthesis
(IWLS), June 2005 (pdf,
slides)
[C37] Yan Meng, Andrew P. Brown, Timothy
Sherwood,
Ronald A. Iltis, Hua Lee and Ryan Kastner, “MP Core: Algorithm
and Design
Techniques for Efficient Channel Estimation in Wireless Applications”, Design
Automation Conference (DAC),
June 2005 (pdf,
slides)
[C38] Wenrui Gong, Yan Meng, Gang Wang, Ryan
Kastner
and Timothy Sherwood, “Data Partitioning for
Reconfigurable Architectures with
Distributed Block RAM” – International Conference on Engineering of
Reconfigurable Systems and Algorithms (ERSA), June 2005 (pdf)
[C39] Ronald A. Iltis, Hua Lee, Ryan Kastner,
Daniel
Doonan, Tricia Fu, Rachael Moore and Maurice Chin, “An Underwater
Acoustic Telemetry Modem for Eco-Sensing” – MTS/IEEE Oceans, September
2005 (pdf,
slides)
[C40] Wenrui Gong, Gang Wang and Ryan Kastner
“Storage
Assignment during High-level Synthesis for Configurable Architectures”,
International
Conference on
Computer-Aided Design (ICCAD),
November 2005 (pdf,
slides)
[C41] Andrew P. Brown, Ronald A. Iltis and
Ryan
Kastner, “Efficient Distributed
Algorithms for Data Fusion and Node
Localization in Mobile Ad-hoc Networks”,
International Conference on
[C42] Yan Meng, Ryan Kastner and Timothy
Sherwood, “Algorithm/Architecture
Co-exploration for Designing Energy Efficient Wireless Channel
Estimator”, Mobile
Computing Hardware Architectures: Design and Implementation (MOCHA), co-located
with the Hawaii International Conference on System Sciences (HICSS), January 2006 (pdf)
[C43] Shahnam Mirzaei, Anup Hosangadi, and
Ryan Kastner,
“High
Speed FIR Filter Implementation Using Add and Shift Method”, International
Symposium on Field Programmable Gate Arrays (FPGA), February 2006 –
poster
presentation
[C44] Ryan Kastner, Wenrui Gong, Adam Kaplan,
Philip
Brisk, Majid Sarrafzadeh, Xin Hao, and Forrest Brewer, “Layout Driven
Data Communication Optimization for High Level Synthesis”, Design,
Automation and Test in Europe Conference (DATE), March 2006 (pdf,
slides)
[C45] Anup Hosangadi, Farzan Fallah and Ryan
Kastner, “Optimizing
High Speed Arithmetic Circuits Using Three Term Extraction”, Design,
Automation and Test in
[C46] Gang Wang, Wenrui Gong, and Ryan
Kastner, “Defect-Tolerant
Nanocomputing Using Bloom Filters” (pdf)
–
Symposium on
Field-Programmable Custom Computing Machines (FCCM), April 2006 – poster
presentation
[C47] Yan Meng, Timothy Sherwood and Ryan
Kastner, “Leakage Power
Reduction of Embedded Memories on FPGAs through Location Assignment”, Design
Automation Conference (DAC),
July 2006 (pdf,
slides)
[C48] Gang Wang, Wenrui Gong, Brian DeRenzi
and Ryan
Kastner, “Design Space
Exploration using Time and Resource Duality with
the Ant Colony Optimization”,
Design Automation
Conference
(DAC), July
2006 (pdf,
slides)
[C49] Theodore Huffmire, Shreyas Prasad,
Timothy
Sherwood and Ryan Kastner, “Policy-Driven Memory
Protection for Reconfigurable Hardware”, European
Symposium on Research in Computer Security (ESORICS), September
2006 (pdf)
[C50] Hua Lee, Tricia Fu, Daniel Doonan,
Christopher
Utley, Ronald A. Iltis and Ryan Kastner, “Design and
Development of a
Software-Defined Underwater Acoustic Modem for Sensor Networks for
Environmental and Ecological Research” –
MTS/IEEE Oceans, September 2006 (pdf)
[C51] Bridget Benson, Grace Chang, Derek
Manov, Brian
Graham and Ryan Kastner, “Design of a Low-cost
Acoustic Modem for
Moored Oceanographic Applications” - International Workshop on
Underwater Networks (WUWNet), September 2006 (pdf,
slides)
[C52] Shahnam Mirzaei, Anup Hosangadi and
Ryan
Kastner, “FPGA Implementation
of High Speed FIR Filter Using Add and
Shift Method” – International
Conference on Computer Design (ICCD), October 2006 (pdf,
slides)
[C53] Daniel Doonan, Tricia Fu, Christopher
Utley,
Ronald A. Iltis, Ryan Kastner and Hua Lee, “Design and
Experimentation
with a Software-Defined Acoustic Telemetry Modem” – International Telemetering
Conference (ITC), October 2006 (pdf)
[C54] Gang Wang, Wenrui Gong and Ryan
Kastner, “On the Use of
Bloom Filters for Defect Maps in Nanocomputing” – International
Conference on Computer-Aided Design (ICCAD), November 2006 (pdf)
[C55] Ronald Iltis, Shahnam Mirzaei, Ryan
Kastner, Richard
E. Cagley and Brad T. Weals, “Carrier Offset and
Channel Estimation
for Cooperative MIMO Sensor Networks”–
IEEE Global Telecommunications Conference
(GLOBECOM), November 2006 (pdf,
slides)
[C56] Shahnam Mirzaei, Ryan Kastner, Richard
E. Cagley
and Bradley T. Weals “Memory Efficient
Implementation of Correlation Function
in Wireless Applications” International Symposium on Field Programmable
Gate
Arrays (FPGA), February 2007
– poster
presentation
[C57] Richard E. Cagley, Brad T. Weals, Scott
A.
McNally, Ronald Iltis, Shahnam Mirzaei and Ryan Kastner,
“Implementation
of the Alamouti OSTBC to a Distributed Set of Single-Antenna Wireless
Nodes”– IEEE Wireless
Communications and Networking Conference (WCNC), March 2007 (pdf,
slides)
[C58] Ted Huffmire, Brett Brotherton, Gang
Wang,
Timothy Sherwood, Ryan Kastner, Timothy Levin, Thuy Nguyen and Cynthia
Irvine,
“Moats
and Drawbridges: An Isolation Primitive for Reconfigurable Hardware
Based
Systems”– IEEE
Symposium on Security and Privacy, May 2007 (pdf)
[C59] Susmit Biswas, Tzvetan Metodiev,
Fredric T.
Chong, Ryan Kastner and Timothy Sherwood, “Efficient Storage of
Defect
Maps for Nanoscale Memory”, Workshop on Non-Silicon Computing held in
conjunction with the International Symposium on Computer Architecture
(ISCA),
June 2007 (pdf,
slides)
Theses
[T1] Ryan
Kastner, “Synthesis Techniques
and
Optimizations for Reconfigurable Systems”, PhD Thesis, Computer Science Department, University of
California, Los Angeles, September 2002 (pdf)
[T2] Ryan
Kastner, “Methods and
Algorithms
for Coupling Reduction”, MS Thesis, Department
of Electrical and Computer Engineering, Northwestern
University, Evanston, IL, August 2000 (pdf)
[T3] Yan
Meng, “Algorithm/Architecture
Design
Space Co-exploration for Energy Efficient Wireless Communications
Systems”,
PhD Thesis, Department of Electrical
and Computer Engineering, University of California, Santa Barbara,
June
2006 (pdf)
[T4] Anup
Hosangadi, “Optimization
Techniques
for Arithmetic Expressions”, PhD Thesis, Department
of Electrical and Computer Engineering, University of
California, Santa Barbara, July 2006 (pdf)
[T5] Ali
Umut Irturk, “Implementation of
QR
Decomposition Algorithm using FPGAs”, MS Thesis, Department of Electrical and Computer
Engineering, University of California, Santa Barbara, June 2007 (pdf)
[T6] Gang
Wang, “Ant Colony
Metaheuristics
for Fundamental Architectural Design Problems”, PhD Thesis, Department of Electrical and Computer
Engineering, University of California, Santa Barbara, July 2007
(pdf)
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